Staff Engineer, Design verification

31 lug - Milano
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Experteer Overview

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As a Staff Design Verification Engineer in the Data Center and Energy group, you will verify complex mixed/digital signal ICs and sub-systems. You will own verification of features from blocks to sub-systems using modern methodologies and mentor junior engineers. Your work will focus on high-speed interfaces, DSP data-paths and verification environments that enable leading-edge power conversion solutions for data centers.

This role offers impact through improving verification flow and driving robust, scalable verification across projects. You will collaborate with cross-functional teams to ensure verification goals support ADI's mission to enable breakthroughs at the Intelligent Edge.

Retribuzione / Benefits

Verify sub-systems using advanced verification methodologies

Develop verification plans and environments from scratch across multiple projects

Validate blocks with SystemVerilog and UVM,



including scoreboard assertions and coverage

Own complex feature verification and mentor junior engineers

Improve verification flow and methodology

Perform gate-level simulations and debugging at the sub-system level

Responsabilità

Bachelor’s or Master’s degree in Electronics Engineering

8+ years in digital design, with at least 3 years in digital verification

Expertise in Verilog, SystemVerilog, UVM; programming and scripting in Perl or Python

Strong understanding xlwpduy of constrained random verification, coverage, and assertions

Test plan development and building verification environments from scratch

Extensive experience with verification of complex blocks, regressions, and coverage closure

Gate-level simulations and debugging

Excellent debugging, analytical, and problem-solving skills

Strong interpersonal, teamwork, and communication skills

Highly independent, proactive, and results-oriented

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