[permanent position] senior verification engineer

01 ago - Italia
SiPearl

About Si Pearl Si Pearl is the European fabless designer of sovereign secure high‐performance energy‐efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy, climate and engineering with a reduced environmental footprint. In June 25, Si Pearl completed the design of the most complex CPU ever designed in Europe, Rhea1. Featuring 80 Arm Neoverse V1 cores and 61 billion transistors, it is currently in production at TSMC. Si Pearl CPUs will equip the two first European exascale supercomputers belonging to Euro HPC JU: Rhea1 will be integrated into the JUPITER machine based in Germany and Rhea2 will be part of Alice Recoque in France. Incubated within the European Processor Initiative (EPI) Consortium and seed‐funded by the European Union, Si Pearl employs almost 200 people across France (Maisons‐Laffitte, Grenoble, Massy, Sophia Antipolis), Spain (Barcelona) and Italy (Bologna). Following a €130 million Series A, the company has launched its Series B round. About the role In this role,



you will work closely with our Verification Team Lead to define and drive the architecture of Si Pearl's microprocessor verification platform. You will play a key role in designing and validating our next‐generation So Cs while leading a team of engineers. What a regular day at the job might look like Define the verification platform architecture (UVM/System Verilog, C/C++, Python...) Develop and maintain test environments, verification benches, and functional simulations Plan, prioritise and track verification activities throughout the development cycle Lead and mentor a team of verification engineers Collaborate with system architects, design teams and embedded software teams What would make you succeed in this role Minimum 7–10 years of experience in ASIC/So C verification, including 3–5 years as an architect or lead Proficiency in System Verilog/UVM, VHDL/Verilog, C/C++, Python/TCL scri

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