Principal Engineer

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/78bl5s

Experteer Overview In this role you will contribute to the development of Marvell's next-generation high-speed PAM/Coherent DSPs and PHYs within a dynamic digital design team. You will define subsystem architecture and micro-architecture, develop RTL and integrate IPs, while collaborating across architecture, verification, and back-end teams to meet quality and performance goals. The work spans from specification to prototype bring-up with influence on overall chip design. This is an opportunity to shape advanced, high-performance hardware for data center and AI/networking applications.
Retribuzione / Benefits Define subsystem architecture, micro-architecture, and register specifications for complex SoCs
Develop efficient RTL using SystemVerilog, perform synthesis, and work with backend resources
Integrate internal and external vendor IPs into designs
Design, debug, and support ICs, IPs, and DFT blocks with quality criteria
Collaborate with architecture, floorplanning, backend, verification, DFT, and STA teams to deliver high-quality hardware
Contribute to RTL development, DFT,



synthesis, static timing, formal verification, CDC analysis, and functional verification
Assist in pre-silicon verification tasks with the Verification team
Support design automation of CAD/EDA flows
Collaborate with post-silicon and software teams for prototype bring-up and performance tuning
Mentor junior team members
Work with cross-functional teams across architecture, design, verification, physical design, and software/firmware
Responsabilità MS/PhD in EE or related field with 10 years of experience
Fluent in RTL coding design techniques (SystemVerilog)
Experience with DFT, resets, LEC, Lint
Experience with multi-clock designs
Experience with synthesis, static timing closure, formal verification, gate-level simulations, block-level functional verification
Experience with test structures for DFT, IP integration, fault models, and coverage techniquesStrong knowledge of ASIC design flow fro

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/78bl5s