Director - Hardware Engineering, AI Infrastructure Systems

01 ago - Italia
Altro

Position Overview
We are looking for an entrepreneurial, technically exceptional engineering leader to establish and run Axelera's AI Infrastructure Systems division within the AI Integrated Systems (AIS) group. This is a new function, created to realize and deliver our next‐generation accelerator silicon into datacenter‐class form factors from PCIe accelerator cards and OAM‐class modules to full 1U/2U rack systems and dense compute nodes targeting enterprise AI, sovereign cloud and HPC customers.
You will build the team, shape the technical roadmap, and own end‐to‐end delivery of board‐and system‐level products for two strategic programmes. You will partner closely with the engineering leadership of the Embedded AI product line within AIS, System and Platform Architecture within R&D;, the silicon organisation, the Voyager SDK/software group, and Axelera's go‐to‐market teams serving hyperscalers, sovereign AI initiatives and the European HPC ecosystem.
This role is deeply hands‐on, owning implementation, validation, and delivery of platform systems.



You will review schematics and layouts, challenge power and thermal budgets, shape the BMC and platform‐firmware stack, and walk the lab floor during bring‐up. Strategic leadership without technical depth will not work here.
Key Responsibilities
Build the Infrastructure Systems engineering team from the ground up: hire, structure and mentor a multidisciplinary organisation covering hardware architecture, PCB design, power/thermal/mechanical engineering, firmware and platform validation with in‐house and 3rd‐party resources
Define the technical roadmap for the division's board‐and system‐level server products—PCIe Gen6/CXL accelerator cards, OAM modules and UBB baseboards, and full 1U/2U rack systems, evolving toward rack‐scale solutions including networking fabric and storage architecture—aligned with the next‐generation system and silicon roadmap.
Serve as the technical authority across system implementation, including s

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