Head of Silicon Design Infrastructure
Pubblicato il 01-08-2026 - Biotecnologie - Farmacia - Chimica in Italia
Fondazione Chips-IT is seeking a Lead of Silicon Design Support Infrastructure to establish and lead the Design, Validation and Test Infrastructure Group. This Group will enable multi-domain semiconductor demonstrator development (Digital, Analog, Power) supporting internal research teams and collaborations with university and industry partners.
The Group will have a central role in the operation of Chips-IT, providing the best possible environment for Research Groups to develop their projects. Its capabilities should bring the Foundation to demonstration levels of TRL 5 to 7 depending on the projects, while also providing infrastructure access for academic and industrial partners within established collaboration frameworks.
The work can be carried out either in Pavia or in Bologna.
KEY RESPONSIBILITIES
Set-Up of the Group
In coordination with the Research Groups Directors, will define and propose to the CEO the organisation of the Silicon Infrastructure Group and present a 3-year budget forecast
Together with the HR Manager, will define the profiles of the personnel,
engineers and technicians, to recruit (initially between 5 and 10 people)
It is expected that the infrastructure will provide the following:
EDA Tool Management: Installing, maintaining, and upgrading EDA software licenses from vendors like Synopsys, Cadence, Siemens, and Keysight for digital, analog, mixed-signal, and power IC design
Computing Infrastructure Optimization: Managing computing environments, including compute clusters, storage, and networking, to support compute-intensive design and simulation workloads across digital, analog, and power domains
Workflow Automation: Continuously developing and optimizing multi-domain design workflows from architecture through tape-out, using advanced tools and techniques to enable efficient silicon demonstrator development
Advanced Design Tools: Evaluating and enabling cutting-edge design automation tools and methodologies across all semiconductor domains