Mems Analog Mixed Signal Verification Sr/Team Leader
Pubblicato il 31-07-2026 - Altro in Bardi
Experteer Overview In this role you will contribute to validating mixed-signal ASICs within the MEMS sGROUP, collaborating across the verification chain from spec to industrialization. You will build and refine test benches, create verification components, and develop regression scenarios to stress analog, digital and mixed?signal designs. You'll apply advanced verification methods at subsystem and SoC levels, shaping robust silicon for cutting?edge MEMS applications. This opportunity combines hands?on debugging with cross?functional teamwork in a globally respected company.
Retribuzione / Benefits Define and develop verification test benches for mixed-signal ASICs
Develop verification components and test cases for simulation
Debug failures and create simulation scenarios for studies
Work with advanced verification methodologies at subsystem and SoC levels
Responsabilità 3-5 years of experience in mixed?signal ASIC verification
Strong knowledge of Analog custom circuit design (e.g., ADC, DAC, comparators)
Experience with analog, digital and mixed?signal simulation environments and tools
Bugs analysis and reporting; Analog SystemVerilog Assertions
Basic knowledge of modeling languages (SystemVerilog, Verilog-AMS) and analog model definition/validation; Coverage
Python scripting; UPF applied to mixed?signal simulations (plus)
Familiarity with SystemVerilog/UVM, Cadence?based tools (plus) and communication protocols (I2C, SPI, I3C)
Version control systems; Formal tools for top?level connectivity (plus)
Soft skills: good communication, fluent in English, team collaboration
#J-*****-Ljbffr