31 lug - Catania
Segment (Twilio)
ppNXP's Industrial IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most.
NXP's advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.
NXP is building new teams in Catania to create high impact micro-controllers (MCU) as part of NXP's intelligent AI at the Edge.
This team will include a wide range of engineering talent from analog to SOC digital design.
Full product development local will product world class products at a world class pace.
This team will include all key engineering disciplines in Analog and Digital Design, Architecture definition, Verification, DfT and Physical Design to produce high performance and quality products.
/ph3Your Responsibilities.
/h3ulliLead and execute the full digital IC design flow for complex System-on-Chip (SOC), including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), formal verification, and power analysis.
/liliContribute to design for testability (DFT) implementation and verification.
/liliCollaborate closely with analog, mixed-signal, and software teams to define interfaces, optimize system performance and ensure seamless integration.
/liliDevelop and implement innovative digital architectures and design methodologies to meet challenging performance, power, and area targets.
/liliPerform comprehensive design verification using simulation tools, formal verification techniques, and hardware emulation.
/liliParticipate in post-silicon validation and debug activities, identifying and resolving issues to ensure product quality.
/liliMentor junior engineers, provide technical guidance, and contribute to continuous improvement of design processes and methodologies.
/liliGenerate detailed design documentation, including specifications,
test plans, and design reviews.
/liliStay abreast of industry trends, emerging technologies, and best practices in digital IC design methodology shared in the team.
/li /ulh3Your Profile.
/h3ulliMaster's degree in Electrical Engineering, Electronics Engineering, or related field.
/liliMinimum of 5+ years of experience in digital IC design.
/liliExpertise in Verilog/SystemVerilog for RTL design and verification.
/liliProven experience with industry-standard EDA tools for synthesis, STA (e.g., Synopsys Design Compiler, Cadence Genus, Primetime), formal verification (e.g., Synopsys Formality), and simulation (e.g., VCS, QuestaSim).
/liliStrong understanding of digital design principles, clock domain crossing (CDC) issues, power integrity, and low-power design techniques.
/liliExperience with scripting languages (e.g., Python, Perl, Tcl) for automation and design flow optimization.
/liliFamiliarity with mixed-signal integration challenges and verification methodologies.
/liliExcellent problem-solving, analytical, and debugging skills.
/liliStrong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment.
/liliAbility to take initiative, work independently, and lead technical discussions.
/li /ulpNXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.
/ppAs of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 50,600 € and 69,600 € annually.
This range is intended as a guideline.
Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs.
/ppThis position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria).
/ppWhere relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.
/ppMore information about NXP in Italy... /p /p #J-*****-Ljbffr
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