Senior Verification Architect - SystemVerilog & UVM Lead

04 ago - Pavia
Infineon Technologies

Infineon Technologies AG in Italy invites a Senior Staff Engineer Verification to shape verification plans for digital blocks in Mixed Signal designs, using SystemVerilog, UVM, and modern verification tools. You will lead and coordinate other verification engineers, execute tests on RTL and gate-level, and mentor junior colleagues.

Collaborating with analog/digital designers and other verification teams, you will help evolve methodologies and flows, contributing to cutting-edge power and IoT

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Agente Immobiliare - Treviso...

09 ago - Treviso
Adecco

Magazziniere - settore edile...

09 ago - Sesto San Giovanni
Adecco

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B-FUTURE CHALLENGE-BOOM

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Field Data Driver & 360° Imaging Specialist

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