Senior Verification Architect - SystemVerilog & UVM Lead

04 ago - Pavia
Infineon Technologies

Infineon Technologies AG in Italy invites a Senior Staff Engineer Verification to shape verification plans for digital blocks in Mixed Signal designs, using SystemVerilog, UVM, and modern verification tools. You will lead and coordinate other verification engineers, execute tests on RTL and gate-level, and mentor junior colleagues.

Collaborating with analog/digital designers and other verification teams, you will help evolve methodologies and flows, contributing to cutting-edge power and IoT

Aiuti per donna disabile

08 ago - Carini
Mary

Tirocinio retribuito

08 ago - Melegnano
Sicurezza e Gestioni

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Personal trainer

08 ago - Napoli
Ilaria

LAVORO a MILANO (Zona Bocconi):

08 ago - Milano
dalia2