Physical Design Manager Engineer

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7a0q4n

ph3bThe Role /b /h3 pAs a Physical Design Manager Engineer, you will serve as the technical reference point for the most complex digital blocks (high‑speed, mixed‑signal control, or automotive low‑power). You will operate at the intersection of logic and physics, ensuring that the functional design intent is preserved and optimized during physical implementation. /p h3bKey Responsibilities /b /h3 ul liStrategic Physical Implementation Constraint Management /li liDrive the entire implementation flow (Floorplanning, PR, Clock Tree Synthesis) with a "constraint‑driven" approach. /li liFunctional Context Analysis: Anticipate routing and timing bottlenecks. /li liDynamic Constraint Management: Analyze, clean, and regenerate timing constraints at every stage (Pre‑Placement, Placement, Pre‑CTS, Post‑CTS, Sign‑off), ensuring they reflect both the physical reality of the silicon and the functional requirements (e.g., Multi‑Cycle Paths, distinguishing real vs. spurious False Paths). /li liTiming Sign‑off ECO Leadership /li liManage complex timing closures (Multi‑clock domains, asynchronous interfaces) using advanced techniques (DMSA, OCV/AOCV/POCV). /li liDrive ECO (Engineering Change Order) strategies not just at the gate level, but by proposing changes when the physical impact requires it. /li liOversee Signal Integrity (SI) and Power Integrity analysis. /li /ul h3bRequirements (Must Have) /b /h3 ul liExperience: 10+ years in the semiconductor industry with a focus on Physical Design and Digital Implementation. /li liConstraint Mastery:



Expert knowledge of the SDC format and the ability to write and debug complex constraints for multi‑mode/multi‑corner (MMMC) designs. /li liTiming Closure: Solid experience in STA (PrimeTime/Tempus), CDC (Clock Domain Crossing) analysis, and managing hold/setup violations in advanced technology nodes or critical automotive contexts. /li liScripting: Excellent automation skills (Tcl, Python, Perl) for report analysis and massive data flow management. /li /ul h3bPreferred Qualifications (Nice to Have) /b /h3 ul liPrevious experience in a digital environment. /li liBackground in Process Integration or knowledge of yield topics (Yield/DFM) and Failure Analysis. /li liExperience with Automotive chips (ISO 26262) or Low Power design (UPF/CPF). /li /ul h3bWhat Do We Offer /b /h3 ul liJoin a highly innovative microelectronics company working at the forefront of RISC‑V and advanced SoC technologies. /li liOpportunity to play a key technical leadership role bridging industry and public research. /li liCollaboration with top‑tier research institutions and industrial partners across Europe. /li liFlexible working conditions and hybrid work environment. /li liCompetitive remuneration aligned with seniority and expertise. /li liPosition based in Rome. /li /ul pAt Openchip Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity. /p /p #J-18808-Ljbffr

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7a0q4n