Principal Functional Verification Engineer

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7acu7n

ph3Principal Functional Verification Engineer /h3 pbRole: /b As a Functional Verification Principal Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level.
Your work will involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.
/p pbKey Responsibilities: /b /p ul liReading and analysing the system requirements and architecture requirement documents.
/li liDeveloping detailed Test and Coverage plans based on the Architecture and Micro-architecture.
/li liDeveloping Verification Methodology, ensuring scalability and portability across environments.
/li liDeveloping Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
/li liExecuting Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.
/li liUsing the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, ...).
/li liCreating and executing test cases to verify the functionality, performance, and robustness in embedded C and SV.
/li liIdentifying, isolating, and debugging issues found during verification, leveraging simulation and debugging tools to root?cause failures and drive resolution with design and architecture teams.
/li liWorking closely with cross?functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.
/li liOrganizing work and deliverables between skills, internal and external teams.




/li liMentoring and training the next generation of verification engineers.
/li liCoordinating functional verification teams.
/li /ul pbRequired Skills and Experience: /b /p ul liMaster Degree in a relevant field.
/li liMinimum 15 years of experience in verification of complex SoC or IP.
/li liExperience in SystemVerilog/UVM.
/li liExperience in SystemC/C++.
/li liExperience in Formal Verification and UPF.
/li liExperience in HW–SW co?verification and simulation.
/li liSome previous experience in firmware?based verification is a good to have.
/li liKnowledge of scripting languages such as Bash, Perl, Python.
/li liExperience using verification management tools.
/li liStrong debugging and problem?solving skills, with the ability to effectively analyze and resolve complex verification issues.
/li liGood level of English, both written and spoken, is mandatory.
/li /ul pbPreferred Qualifications: /b /p ul liExperience in firmware?based verification.
/li liInsights of NOC and other IPs or standard peripherals such as PCIe, DDR, HBM.
/li liTeam player, able to work with multiple cultures both on site and remotely.
/li liAutonomous and flexible is mandatory.
/li liStrong leadership and communication abilities.
/li /ul pbWhat We Offer: /b /p ul liJoin an innovative team and experience company growth.
/li liWe believe in investing in our employees and providing them with opportunities to grow and develop their careers.
/li liEnjoy a hybrid work environment.
/li liWe offer flexible scheduling.
/li liWe provide a remuneration that values your experience.
/li liThe position will be based in Rome.
/li /ul pWe are a diverse and inclusive team.
We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.
/p /p #J-*****-Ljbffr

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7acu7n