11 ago - Modena
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Job Overview
To strengthen our IC design team, we are looking for a junior digital IC designer. The role involves design, simulation, and full validation of several programmable functional units within the IC device that constitutes the core of the Eggtronic power adapter. You will work closely with the R&D; team to develop new IPs for the next generation ASICs.
Responsibilities
Design in VHDL/Verilog/System‑Verilog at RTL level of core functional blocks
Implement RTL-to-synthesis IC design flow, including timing and power analysis
Design testbenches in System‑Verilog (UVM compliant) and verify digital IPs using simulation tools from RTL to post‑layout
Co‑simulate digital and analog IPs to validate the complete mixed‑signal system
Prototype core digital IPs on FPGA
Participate in silicon validation activities using laboratory instrumentation
Qualifications and Background
PhD or MS Degree in Microelectronics or Physics
1‑10 years of related experience
Strong knowledge of CMOS technology, standard logic libraries, and manufacturing processes
Good knowledge of VHDL, Verilog, or System‑Verilog
Basic knowledge of programming and scripting languages such as C++, TCL, bash, Perl
Experience translating design requirements into RTL descriptions
Experience with digital or mixed‑signal verification activities, testbench design, verification planning, and regression testing
Strong understanding of the complete ASIC design flow (RTL to GDSII)
Proficiency with EDA tools such as Cadence or Synopsys Design Framework
Good English written and spoken skills
Nice to Have
Basic knowledge of modelling languages like Verilog‑A or VHDL‑AMS
Knowledge of microprocessor design (architecture, custom ISA definition, implementation of data/memory bus)
Benefits
Competitive salary
Employee fringe benefits (welfare)
Dedicated healthcare check‑up
Annual premio
Talented team
Career opportunities
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