Senior Silicon Physical Design Engineer
Pubblicato il 12-08-2026 - Axelera AI in Monza
Senior Engineer - Silicon Physical Design (Italy based)
L'esperienza richiesta ai candidati, così come le competenze e le qualifiche aggiuntive necessarie per questo lavoro, sono elencate di seguito.
Apply for the Senior Engineer - Silicon Physical Design (Italy based) role at Axelera AI.
About Us
Axelera AI is not your regular deep-tech startup. We are creating the next‑generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years we have raised a total of $120 million and built a world‑class team of 220+ employees (including 49+ PhDs with more than 40 000 citations), both remotely from 17 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our Metis™ AI Platform, which achieves a 3‑5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer.
Are you up for the challenge?
Position Overview
As a Senior Silicon Physical Design Engineer at Axelera AI you will play a crucial role in developing cutting‑edge multi‑core in‑memory compute SoCs. Leveraging your expertise in ASIC Physical Design from RTL to GDS, you will be responsible for synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR sign‑off and formal verification. You will collaborate closely with architecture and RTL teams to ensure successful project execution.
Key Responsibilities
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- Perform synthesis, floorplanning, place and route, extraction, timing analysis and physical verification.
- Ensure timing closure, constraint generation and optimisation.
- Execute clock tree synthesis (CTS) and clock‑building techniques.
- Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics and analog IPs.
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