Senior Staff Engineer Verification

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Join the thinkers, builders, and problem-solvers behind tomorrow's technology.

As a Senior Staff Engineer Verification (f/m/div) in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.
Are you in?Your RoleKey responsibilities in your new roleCreate and define verification plans, for digital verification of Mixed Signal designsCreate new and improve existing verification environments in SystemVerilog language using Universal VerificationMethodology (UVM)



and Constrained Random approachExecute tests in these environments on RTL and gate-level and debug issues in design and verification environmentsLead and coordinate other verification engineers in projectsClosely cooperate with analog and digitaldesigners as well as concept and other verification engineersMentoring of junior colleagues, consultants and studentsContribute to enhancement of existing methodologies and flows, by driving required innovation projectsYour ProfileQualifications and skills to help you succeedA university degree in Electrical Engineering, Computer Science, Information Technology or a similar academic discipline6+ years of experience in Digital Verification.

Experience with leadership responsibilities as a plus Excellent know-how in System Verilog, UVM, and verification tools: Xcelium, Verdi and vManager or similarGood knowledge of RTL design (HDL) and digital or mixed-signal circuits Knowledge of GIT, Python, and other programming languages as a plusWe offer competitive salaries and additional benefits based on your performance, experience and qualification.

The employment is in accordance with the collective salary and wage agreement fo

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7d9r9w