Senior Engineer Functional Verification

12 ago - Roma
Openchip & Software Technologies

The Role

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As a Senior Functional Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.

Key Responsibilities

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- Reading and analysing the system requirements and architecture requirement documents.
- Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
- Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.
- Using the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, …).
- Create and execute testcases to verify the functionality,



performance, and robustness in embedded C and SV.
- Identify, isolate, and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams.
- Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.
- Participation to verification methodology improvements.
- Organize work and deliverables between skills, internal and external teams.
- Opportunities for mentoring and training the next generation of verification engineers.

Qualifications

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- Master Degree in relevant field.
- Min 7 years of experience in relevant field of Verification of complex SoC or IP.
- Experience in SystemVerilog/UVM.
- Experience in SystemC/C++.
- Experience in Constrained random

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