Design layout Engineer
Pubblicato il 12-08-2026 - MICRON in Avezzano
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever..Department IntroductionThe Non-Volatile NAND Design Engineering group is responsible for the design and optimization of analog, digital and mixed-signal circuits enabling advanced NAND Flash memory products. Close collaboration with multi-functional teams ensures scalable, manufacturable, and reliable solutions across technology nodes.Role OverviewAs a Layout Design Engineer at Micron Semiconductor Italia, you will play a critical role in the physical implementation of advanced NAND Flash products, working across analog, custom digital, and mixed‑signal circuits.Beyond traditional layout excellence, this role places strong emphasis on automation, AI‑assisted methodologies, and data‑driven layout optimization, which are central to Micron’s future design strategy.
You will actively contribute to evolving the layout field from manual execution toward scalable, high‑productivity, and intelligent build approaches.ResponsibilitiesResponsibilities include, but not limited to:•
Design and implement complex analog, mixed-signal, and custom digital layout blocks (e.g., charge pumps, regulators, oscillators, IO, sensors).•
Perform layout integration activities including floorplanning, placement, routing, and parasitic-aware optimization.•
Support design validation through parasitic extraction, simulation correlation, silicon learning, and tape-out revisions.•
Collaborate with multi-functional teams (build, CAD, modeling, product engineering) to ensure manufacturability, quality, and performance targets.•
Develop and drive automation and AI-assisted layout methodologies (e.g., parameterized layout, scripting, data-driven optimization).•
Contribute to methodology improvement,