ph3Responsibilities /h3ulliLead the Digital Design team from specification definition to successful silicon bring‑up /liliDesign digital components for advanced Analog/Mixed‑Signal IPs, including high‑speed SerDes, PHYs, and PLLs /liliOwn digital signoff activities across the full flow (RTL‑to‑GDS, LEC, linting, CDC/RDC, ATPG) /liliCollaborate closely with System Architecture teams to define and implement complex digital functions (e.g., adaptive channel equalization) /liliPartner with Analog Design teams to ensure seamless digital control and integration of analog blocks /liliWork alongside Digital Physical Design teams to achieve robust timing closure and clean signoff /liliEngage with internal customers and Verification teams to drive high‑quality IP definition, integration, and design excellence /li /ulh3Qualifications /h3ulli10+ years of experience in RTL design for Analog/Mixed‑Signal IPs /liliStrong leadership mindset with the ability to guide and inspire engineering teams /liliExpert‑level proficiency in Verilog/SystemVerilog /liliSolid understanding of the full digital design flow (RTL‑to‑GDS, LEC, linting, CDC/RDC, ATPG)

/liliGood knowledge of Digital Test Methodologies /liliExperience in high‑speed SerDes is highly valued /liliFluency in English (mandatory) /li /ulh3Location and Compensation /h3pPavia, Italy /ppIndicative Salary Range: 57,600€ - 79,200€ /ppThe stated salary comprises annual base pay and target variable compensation. The starting salary is determined using objective, gender neutral criteria, including relevant experience, qualifications, and role scope; prior compensation is not requested or considered. Employees also benefit from a comprehensive total rewards package, which may include further compensation and agevolazioni elements depending on local regulations and company policies. /ph3Equal Employment Opportunity Statement /h3pWe celebrate diversity and inclusion, welcoming everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect, and tolerance and are committed to give all applicants and employees equal opportunities. /p /p #J-18808-Ljbffr

Principal Digital Design Engineer (f/m/div)

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