Senior Validation Engineer
Pubblicato il 13-08-2026 - Altro in Italia
The Post-Silicon Validation team within the Performance Computing Power Division is building a world-class organization of highly skilled engineers across multiple global sites. Our mission is to push the boundaries of silicon validation for industry-leading integrated circuits enabling high-power, high-efficiency power management systems.
We are committed to delivering the highest level of validation quality by continuously improving test coverage, measurement accuracy, repeatability, automation, and execution efficiency while reducing overall validation time.
As a Senior Validation Engineer, you will be part of a multidisciplinary global development team and play a key role in ensuring that every new product fully meets its electrical, functional, and performance specifications before release to production. You will work closely with Design, Applications, Product Engineering, Quality, and System teams to identify, debug, and resolve silicon and system-level issues while supporting aggressive product development and New Product Introduction (NPI) schedules.
For our new Design Center in Catania, we are looking for a passionate engineer who thrive on innovation, enjoy solving complex technical challenges, and is committed to delivering high-quality results in a fast-paced environment.
Responsibilities: Validate analog, digital, mixed-signal, and power management ICs against electrical, functional, and performance specifications.
Define validation methodologies, develop comprehensive validation plans, and ensure complete feature coverage.
Design, develop, and optimize advanced laboratory test setups for complex silicon evaluation.
Design custom evaluation boards and supporting hardware for silicon characterization.
Develop automated validation frameworks and measurement scripts using Python.
Perform data acquisition, statistical analysis, result correlation, and preparation of detailed technical reports.
Evaluate silicon performance at device, board, and system level,