Junior IC Verification Engineer | Gate‐Level to System Verif
Pubblicato il 13-08-2026 - Eggtronic in ModenaEggtronic srl. Non è sicuro/a delle competenze necessarie per questa opportunità? Legga la descrizione completa qui sotto per avere un quadro completo dei requisiti richiesti. is seeking a junior IC Verification Engineer to join the IC team in Modena, Italy. In this role, you will be responsible for performing gate-level and mixed-signal simulations, as well as block level and system-level verification. Essential qualifications include a basic knowledge of HDL languages (SystemVerilog, Verilog, VHDL), scripting languages like Tcl and Python, and firmware development. xivgfpx The role also offers employee fringe benefits, healthcare check-ups, an annual premio, and a friendly working environment.