Principal Digital Design Engineer

13 ago - Pavia
Infineon Technologies

Responsibilities
- Lead the Digital Design team from specification definition to successful silicon bring‐up
- Design digital components for advanced Analog/Mixed‐Signal IPs, including high‐speed SerDes, PHYs, and PLLs
- Own digital signoff activities across the full flow (RTL‐to‐GDS, LEC, linting, CDC/RDC, ATPG)
- Collaborate closely with System Architecture teams to define and implement complex digital functions (e.g., adaptive channel equalization)
- Partner with Analog Design teams to ensure seamless digital control and integration of analog blocks
- Work alongside Digital Physical Design teams to achieve robust timing closure and clean signoff
- Engage with internal customers and Verification teams to drive high‐quality IP definition, integration, and design excellence

Qualifications
- 10+ years of experience in RTL design for Analog/Mixed‐Signal IPs
- Strong leadership mindset with the ability to guide and inspire engineering teams
- Expert‐level proficiency in Verilog/SystemVerilog
- Solid understanding of the full digital design flow (RTL‐to‐GDS, LEC, linting,



CDC/RDC, ATPG)
- Good knowledge of Digital Test Methodologies
- Experience in high‐speed SerDes is highly valued
- Fluency in English (mandatory)

Location and CompensationPavia, Italy
Vuole candidarsi? Legga tutte le informazioni su questa posizione qui sotto, poi prema il pulsante per candidarsi.Indicative Salary Range: 57,600€ - 79,200€
The stated salary comprises annual base pay and target variable compensation. The starting salary is determined using objective, gender neutral criteria, including relevant experience, qualifications, and role scope; prior compensation is not requested or considered. Employees also agevolazioni from a comprehensive total rewards package, which may include further compensation and benefit elements depending on local regulations and company policies. xivgfpx
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