Principal Engineer
Pubblicato il 13-08-2026 - 73 Marvell Technology Italy in Pavia
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell’s high-speed DSPs are at the forefront of developing a PAM/Coherent ecosystem, providing low-power, high-performance solutions for cloud data center infrastructure, service providers, AI networks, enterprises, and 5G.
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.
You will be part of a highly-skilled,
dynamic team driving the development of Marvell’s next-generation high-speed PAM/Coherent DSPs and PHY designs, which utilize cutting-edge CMOS technology.
As a member of a digital design team, you will be assisting in chip design working closely with architecture team, verification team, supporting back-end teams and timing closure.
What You Can Expect
- Define the sub system architecture, micro-architecture and register specifications for highly complex SoCs. Drive and participate in specification writeup
- working with the architecture team to understand the feature enhancement needs
- Develop overall efficient RTL using (System)Verilog, synthesis, and backend resources.
- Integrate internal and external vendor IPs.
- Design, debug, and support ICs, IPs and block DFT
- Ensuring all quality criteria is met.
- Work closely with the architecture, floorplanning, backend, verification, DFT, STA teams and