Principal engineer functional digital design verification (f/m/div)

13 ago - Pavia
Infineon Technologies

#We Are In for jobs that impact everyone's life. Build the future nobody's dreamed of yet... are you ready to rethink the impossible? As a Principal Engineer Functional Digital Design Verification (f/m/div) in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Are you in?Your Role Key responsibilities in your new role Lead the digital verification of complex digital and mixed signal designs, including IPs, Subsystems, ASIC and So Cs, coordinating activities such as verification planning, verification tracking and reporting, as well as requirement-based verification Collaborate with cross-functional teams, including concept, design, AMS verification, and post-silicon validation teams, to ensure high quality designs Hands-on contributor to digital verification either from scratch, or using legacy verification environments and flows Focus on all-directions-reuse of the Verification Components to be implemented Identify and mitigate risks in dynamic projects, with proactive communication to the project team Drive the improvements of existing verification processes, methodologies and flows, drive required innovation projects, focusing on efficiency improvement,



and get buy-in from management As a technical lead inspire and mentor junior verification engineers while providing invaluable technical support and guidance to development teams and business partners Your Profile Qualifications and skills to help you succeed A University Degree (Master or above) in Electrical Engineering, Physics, Material Science or equivalent8+ years of Digital Verification experience and a deep understanding of all technical aspects of Verification for Mixed-Signal Designs, including 3+ years of leadership activities Outstanding Expertise in digital verification and all tasks needed to achieve design verification closure, including state of the art tools and methodologies (SV-UVM, Xcelium, v Manager, Certitude, etc. A sense of urgency for upcoming innovation in the field of verification Proven leadership skills, with experience in coordinating activities, providing technical guidance, and mentoring junior engineers Self-motivated, flexible, good communication with interpersonal skills and is a good team playerwho can work well with both internal and external partners Proven ability to achieve results in a very dynamic, multi-site environment and be able to coordinate with priorities ands elf-initiatives We offer competitive salaries and additional benefits based on your performance, experience and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group I ().

The monthly salary is paid 14 times p.a.

We offer a higher compensation depending on your expertise and skills. Contact:

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