Physical Design Engineer
Pubblicato il 15-08-2026 - Altro in Catania
We are looking for a Physical Design Engineer to join our Analog Backend team and work on the digital island implementation within our analog chips. This role is ideal for someone who enjoys solving complex physical design challenges in mixed-signal environments.
What You'll Do
Implement key aspects of the ASIC physical design flow, including floorplanning, placement optimization, clock tree synthesis, routing, and physical verification
Optimize designs for performance, reliability, and manufacturability
Perform chip-level power integrity analysis across multiple voltage domains (IR drop, signal EM, and power EM)
Work on digital implementation embedded in analog environments
Collaborate with global cross-functional teams including analog designers and verification engineers
Qualifications
Experience in ASIC Physical Design
Strong understanding of floorplanning, placement, CTS, routing, and sign-off checks
Knowledge of power integrity analysis (IR drop and electromigration)
A team player who enjoys working in an international, collaborative environment
Analog Layout experience is a plus
Additional Information
Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.
With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ' To Make Our Lives Easier .'
At Renesas, you can:
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