Principal Engineer Functional Digital Design Verification
Pubblicato il 15-08-2026 - Elettrotecnica in Pavia
WeAreIn for jobs that impact everyone's life. Build the future nobody’s dreamed of yet... are you ready to rethink the impossible? As a Principal Engineer Functional Digital Design Verification (f/m/div) in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?Your RoleKey responsibilities in your new roleLead the digital verification of complex digital and mixed signal designs, including IPs, Subsystems, ASIC and SoCs, coordinating activities such as verification planning, verification tracking and reporting, as well as requirement-based verificationCollaborate with cross-functional teams, including concept, design, AMS verification, and post-silicon validation teams, to ensure high quality designsHands-on contributor to digital verification either from scratch,
or using legacy verification environments and flowsFocus on all-directions-reuse of the Verification Components to be implementedIdentify and mitigate risks in dynamic projects, with proactive communication to the project teamDrive the improvements of existing verification processes, methodologies and flows, drive required innovation projects, focusing on efficiency improvement, and get buy-in from managementAs a technical lead inspire and mentor junior verification engineers while providing invaluable technical support and guidance to development teams and business partnersYour ProfileQualifications and skills to help you succeedA University Degree (Master or above) in Electrical Engineering, Physics, Material Science or equivalent8+ years of Digital Verification experience and a deep understanding of all technical aspects of Verification for Mixed-Signal Designs, including 3+ years of leadership activitiesOutstanding Expertise in digital verification and all tasks needed to achieve design verification closure, including state of the art t