Staff Embedded Software Engineer
Pubblicato il 15-08-2026 - StudySmarter in Padova
WeAreIn for jobs that impact everyone's life. Join the thinkers, builders, and problem-solvers behind tomorrow’s technology. As a Staff Embedded Software Engineer in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.
Key responsibilities
- Drive embedded software development projects with a strong focus on quality, time‑to‑market and technology trend.
- Collaborate closely with Business Lines and adjacent domains like system and application engineering.
- Design and develop embedded software in the field of embedded systems, prototyping software ecosystems and robotic systems.
- Proactively contribute to the strategy for technology trends in the areas of embedded software and prototyping ecosystems.
- Effectively capture, analyze and understand requirements and break down into structured work packages.
- Align with internal and external stakeholders and represent Infineon at events such as trade fairs and university fairs.
- Support and facilitate mentorship and coaching of embedded software (junior) experts to develop leadership skills.
Qualifications & skills
- A degree in Electrical Engineering, Robotics, Computer Science or a comparable discipline; PhD is a plus.
- At least 5 years of professional experience in embedded software design and development, preferably in semiconductor industry and robotics, with strong proficiency in C, C++ and Python.
- Professional experience in ROS 2 and micro‑ROS, as well as in micro‑ROS enablement and simulation tools (Isaac Sim, MuJoCo).
- Experience with embedded system development flow and tools (Git, build system, GitLab, etc.) and with RTOS (Zephyr, FreeRTOS).
- Very good knowledge of MCU architecture/operation (interrupts, IPC, etc.) and communication peripherals (Ethernet, CAN, UART, SPI, etc.). Experience with ARM Cortex, TriCore and/or RISC‑V architecture is