Senior CAD Semiconductor Engineer

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MissionDefine, deploy, and maintain EDA tool flows and CAD infrastructure supporting semiconductor design and verification activities across full SoC lifecycle.

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Drive the evaluation, benchmarking, and integration of EDA tools (Cadence, Synopsys, Siemens EDA, Arteris) and associated flows to maximize productivity, reliability, and scalability.
Own the engineering infrastructure environment (compute, storage, licensing, CI/CD, automation) required for advanced chip design workloads.
Collaborate with design, verification, and physical implementation teams to ensure efficient, robust, and scalable tool usage.
Explore and integrate AI/ML-based tooling and workflows to improve engineering productivity (automation, debugging, optimization, knowledge extraction).
Ensure optimal trade-offs between performance, cost, scalability, and usability of the CAD environment.
Act as a key technical interface between internal engineering teams, management, and EDA vendors.




Provide regular reporting on tool performance, usage, and roadmap alignment.
Main ResponsibilitiesDefine, deploy, and maintain EDA flows for digital, mixed-signal, and verification activities (simulation, synthesis, P&R;, DFT, signoff).
Evaluate, benchmark, and qualify new EDA tools, releases, and methodologies before production deployment.
Design And Operate EDA Infrastructure Environments, Including
- Compute farms (Linux-based clusters for simulation and regression)
- Storage systems (NFS, distributed storage, backup/DR)
- License servers (FlexLM/Flexera)

Develop And Maintain Automation Frameworks For
- Tool installation and configuration
- Regression and CI/CD pipelines
- Resource provisioning and monitoring

Implement and manage CI/CD pipelines (e.g., Jenkins, GitLab CI) for design and verification workflows.
Collaborate With Engineering Teams To
- Optimize tool usage and flows
- Debug tool

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7g2yqj