FPGA Engineer – Satellite Communications
Pubblicato il 17-08-2026 - EVEREC in Bari
FPGA Engineer – Satellite Communications & DSP Systems – Bari, Apulia – €DOE Verifichi che le sue competenze e la sua esperienza corrispondano ai requisiti di questo ruolo, quindi si candidi con il suo CV qui sotto.Location: Bari, Apulia, Italy (Hybrid working available)
Salary: From €32,000 RAL + stock option plan
Overview:
A high-growth space technology company is seeking an experienced FPGA Engineer to join its core engineering team, developing next-generation satellite communication systems used across disaster response, emergency management, space monitoring, and defence applications.
This role sits at the heart of the company's technology stack, with full ownership of FPGA-based digital architectures – from initial system definition through to hardware validation. You will work in a multidisciplinary team combining DSP, FPGA, RF, and embedded software expertise, contributing directly to mission‐critical satellite platforms.
Key Responsibilities:
- FPGA Design & DSP Implementation
- Design and optimise advanced RTL architectures in VHDL for Xilinx Series‐7 and UltraScale+/FPGAs
- Implement and optimise DSP algorithms for digital and RF communication systems, including filtering, modulation/demodulation, and synchronisation
- Translate high‐level system and DSP requirements into efficient FPGA implementations
- Perform simulation, testing, debugging, and performance verification using FPGA simulation tools and hardware test benches
- Support timing constraint definition and timing closure in complex FPGA designs
- Validate designs on real hardware and contribute to system‐level performance analysis
- System Integration
- Support integration across multiple hardware boards and subsystems
- Contribute to end‐to‐end system validation and bring‐up activities
- Collaborate closely with DSP, embedded software, and system engineers to ensure robust end solutions
- Technical Documentation
- Produce clear technical documentation covering architectures, test results, and