Principal functional verification engineer
Pubblicato il 16-08-2026 - Openchip & Software Technologies in Roma
Ph3The Role /h3 pAs a Functional Verification Principal Engineer, you will be interfacing with architecture, de-sign, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work will involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support. /p h3Key Responsibilities /h3 ul liReading and analysing the system requirements and architecture requirement documents. /li liDeveloping detailed Test and Coverage plans based on the Architecture and Micro-architec-ture. /li liDeveloping Verification Methodology, ensuring scalability and portability across environ-ments. /li liDeveloping Verification environment development and maintenance in SystemVeri-log/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage. /li liExecuting Verification Plans, including Design Bring-up, DV environment Bring-up, Regres-sions and Debug of the test failures. /li liUsing the standard tools and flows of the verification process (Simulators, Coverage Analyz-ers, Unix, Continuous Integration, Bug Tracking, …). /li liCreate and execute testcases to verify the functionality, performance, and robustness in em-bedded C and SV. /li liIdentify, isolate, and debug issues found during verification, leveraging simulation and debug-ging tools to root-cause failures and drive resolution with design and architecture teams. /li liWork closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verifi-cation activities. /li liOrganize work and deliverables between skills, internal and external teams. /li liMentoring and training the next generation of verification engineers. /li liCoordinating functional verification teams. /li /ul h3Required Skills And Experience /h3 ul liMaster Degree in relevant field.
/li liMin 15 years of experience in relevant field of Verification of complex SoC or IP /li liExperience in /li liSystemVerilog/UVM /li liSystemC/C++ /li liExperience in Constrained random, Functional Coverage development, design debug. /li liExperience in Formal Verification, UPF. /li liExperience in HW-SW co-verification and simulation. /li liSome previous experience in Firmware based verification is a good to have. /li liSome knowledge of scripting languages like Bash/Perl/Python. /li liUse of verification management tools. /li liStrong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues. /li liGood level of English, both written and spoken is mandatory. /li /ul h3Preferred Qualifications /h3 ul liExperience in Firmware-based verification. /li liKnowledge in metrics-driven verification. /li liInsights of NOC and other IPs or standard peripherals like PCIe, DDR, HBM … /li /ul h3Soft Skills /h3 ul liTeam player, able to work with multiple cultures both on site and remotely. /li liAutonomous and flexible is mandatory. /li liStrong Leadership and Communication abilities. /li /ul h3What do we offer? /h3 ul liJoin an innovative team and experience company growth. /li liWe believe in investing in our employees and providing them with the opportunities they need to grow and develop their careers. /li liEnjoy a hybrid work environment. /li liWe also offer flexible schedule. /li liWe offer a remuneration that values your experience. /li liThe position will have the base in Rome. /li /ul h3We are looking for outstanding people willing to join our mission to change this industry and help to build a better world. /h3 pAt bOpenchip Software Technologies S.L. /b, we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity. /p /p #J-18808-Ljbffr
