RF Hardware Electronics Designer
Pubblicato il 17-08-2026 - Kurs Orbital in Torino
Location:
Torino, Italy (On-site)
Position Type:
Mid–Senior Level
Contract Type:
Full-time, Permanent
Start Date:
As soon as available
POSITION OVERVIEW
Kurs Orbital is a Turin-based deep-tech company developing autonomous Rendezvous, Proximity Operations and Docking (RPOD) systems for satellite servicing and active debris removal. Our X-band AESA RADAR is the core sensing technology for our ARCap proximity navigation kit, with an in-orbit demonstration target of 2027. You will join a small, senior technical team and take full ownership of flight-bound hardware.
We are seeking a Hardware Electronics Designer to own the design, build, and bring-up of the RF front-end electronics and antenna hardware for our in-house X-band AESA radar payload, used for in-orbit Rendezvous and Proximity Operations (RPO) and Close Proximity Operations (CPO). At Kurs Orbital the RF front-end and the radar algorithms are the core in-house know-how; this role owns the hardware side end-to-end and coordinates subcontractors for the non-core boards and integration.
Power electronics and back-end data/power boards are subcontracted to specialist partners; the role defines requirements and coordinates procurement for these units but does not design them.
The position is primarily on-site in Turin; occasional remote work is possible by arrangement.
KEY RESPONSIBILITIES
- Lead the design of the RF/microwave front-end: T/R modules, LNAs, power amplifiers, filters, mixers, switches, and the beamforming network.
- Design the AESA antenna / phased array and feed network, including beam-steering and beamforming hardware.
- Produce RF PCB designs: RF distribution network, filters, controlled-impedance stack-ups, RF routing, grounding and shielding, EMC/ESD design, and cavity / RF-resonance mitigation.
- Define and implement calibration approaches for the phased array and the RF chain.
- Lead hardware integration verification and validation from the strategy (V&V; Plan, Test Plan preparation) up