Senior Design Engineer H/F
Pubblicato il 19-08-2026 - YO IT Group in Italia
Design Verification Engineer - VLSI/ASIC/FPGA HardwareExperience: 3 - 25 YearsLocation: Permanent Remote anywhere in the WorldContract Length: 6 MonthsType: Tempo pieno contract (8 hrs/day) Overlap Hours: 4 hrs/day with PSTMandatory Skills:Overall - 5 years of experience.Minimum of 2 years of relevant experience in Hardware Design and/or Hardware Verification.Experience With One Or More On The List Below:ASICVLSIFPGASOCExperience with one or more on the list below:SystemVerilog developmentVerilog developmentTestbench development and/or verification.Good communication skills in English.LLM experience is not mandatory; however, the candidate should be fine to work as a LLM Engineer for Verilog.Must-Have:BS or MS degree in Electrical Engineering or related field.3-5 years of proven experience in hardware design development.Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC.Expertise in scripting, front-end and verification workflows,
and integrations within the hardware design environment.Expertise in UVM environments.Expertise in Formal Verification.Expertise in Lint process and refinement.Good communication skills in English.Job Description:We're searching for an exceptional hardware design Developer to play a pivotal role in using the hardware design platform to generate the training data to enhance enterprise LLMs' capabilities. This unique position offers the chance to directly contribute to the sophistication of enterprise LLMs, ensuring they operate with unparalleled efficiency and intelligence.Your Mission:Develop, configure, and customize the hardware design platform, utilizing it to generate vital training data for enterprise LLMs.Liaise with research teams to translate requirements into actionable data insights, directly impacting our LLMs' performance.Uphold the highest standards in coding, debugging, and documentation, ensuring the hardware design solutions are optimized for LLM training and benchmarking.Collaborate across teams to identify