Layout Design, Principal Engineer

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7hto3i

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You bring extensive experience in analog and mixed-signal layout, understanding that successful circuit implementation requires careful attention to routing, matching, shielding, and physical design constraints. Your technical depth spans multiple layers of layout complexity, from current density analysis to matching arrays that maintain performance across process corners. Working with SERDES architectures, you understand critical signal paths, clock distribution requirements, and comprehensive ESD protection strategies.

You are prepared to take ownership of top-level blocks, collaborate with layout teams across geographies, and provide technical guidance through design reviews. At Synopsys, you will contribute to complex IP solutions that meet stringent customer requirements.

What You'll Be Doing

Design and own analog and mixed-signal layout for SERDES IP blocks including RX, TX, and PLL subcircuits in advanced technology nodes

Optimize layout for signal integrity through differential routing, clock and data path management, and parasitic control





Implement ESD design constraints and latch-up mitigation across mixed-signal designs

Develop custom digital logic cell layout with associated routing to meet performance specifications

Execute layout using Custom Compiler and perform verification with ICV, Calibre, Star-RCXT, and PERC

Provide technical leadership through layout reviews and mentorship of engineering team members The Impact You Will Have

Enable SERDES IP deployment in customer silicon across multiple foundries and technology nodes

Ensure signal integrity and reliability standards that determine analog block performance in production

Establish technical standards and best practices for layout design across the team

Implement protection strategies that safeguard customer designs from field failures

Accelerate IP portability and time-to-market through efficient design-for-porting methodologies

What You'll Need

MSEE or BSEE with at least 10+ years of related experience in analog and mixed-signal layout design In depth familiarity with layout of analog and mixed-signal CMOS circuits

Experience in development of SERDES subcircuit layout including RX, TX, PLL, and related blocks

Experience in layout design techniques: optimization for signal integrity including clock and data routes, differential routing, and shielding

Implementation of ESD design constraints and latch-up risk mitigation

Familiarity with custom digital layout including logic cell layout and associated logic path routing





Layout design for reliability including electromigration, IR drop, and related constraints

Design to optimize for parasitic layout effects including matching, reliability, and proximity effects

Familiarity in design for porting techniques

Full custom analog layout design tool experience with Custom Compiler or equivalent

Verification tools experience with ICV, Calibre, Star-RCXT, and PERC

Experience in working with Jira or Atlassian tools or similar project management platforms

Proven understanding of MS Office Suite of applications

Exposure to scripting languages including TCL, PERL, or similar

Who You Are

You apply technical expertise to resolve complex layout challenges across diverse technology nodes

You operate effectively with minimal supervision while maintaining strong collaboration with global engineering teams

You contribute technical mentorship that enhances team capabilities and design quality

You represent engineering excellence in cross-functional and organizational initiatives The Team You'll Be Part Of

You will join the Solutions IP Design Group, developing IP across various technology nodes and foundries for diverse customer applications. The team collaborates locally and globally on complex mixed-signal designs utilizing Synopsys industry-leading tools and methodologies. Our Silicon IP business delivers comprehensive IP portfolios including logic, memory, interfaces, analog, security, and embedded processors that enable customers to accelerate product development and reduce risk.

Remote work is optional for this position.

Rewards And Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7hto3i