Physical Design Senior Engineer
Pubblicato il 21-08-2026 - Openchip & Software Technologies in Roma
The Role As a Physical Design Senior Engineer , you will take technical ownership of the implementation for highly complex digital blocks, including high-speed interfaces, mixed-signal control logic, and automotive low-power modules. Working at the intersection of logic and physics, you are responsible for ensuring that the functional design intent is fully preserved while being highly optimized during the physical implementation phase.
Advanced Physical Implementation & Constraint Ownership
Full-Flow Execution: Take technical ownership of the RTL-to-GDSII implementation, including Floorplanning, Place and Route (P&R;), and Clock Tree Synthesis (CTS).
Bottleneck Resolution: Analyze functional contexts to identify and resolve routing congestion and timing bottlenecks proactively.
Hands-on management of SDC constraints at every stage; Timing Closure & ECO Implementation
Sign-off Focus: Deliver complex timing closure for designs with multiple clock domains and asynchronous interfaces using DMSA and OCV/AOCV/POCV techniques.
Implement Engineering Change Orders (ECO)
at the gate level and propose physical-level adjustments when required to meet timing or power targets.
Design Integrity: Perform and validate Signal Integrity (SI) and Power Integrity (IR-Drop/EM) analyses to ensure robust sign-off.
Experience: 10+ years of professional experience in Semiconductor Physical Design and Digital Implementation.
Expert knowledge of SDC format with the ability to write, debug, and manage complex constraints for Multi-Mode Multi-Corner (MMMC) designs.
Timing & STA: Solid hands-on experience with STA tools (PrimeTime or Tempus) and managing violations in advanced technology nodes or critical environments (e.g., CDC Knowledge: Proficiency in Clock Domain Crossing (CDC) analysis and verification.
Excellent scripting capabilities (Tcl, Python, or Perl) for flow automation and report analysis.
Proven experience interfacing with Front-End teams to optimize RTL for better physical synthes