[Permanent position] Senior verification engineer
Pubblicato il 21-08-2026 - Altro in Bologna
About SiPearl SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy, climate and engineering with a reduced environmental footprint.
In June 25, SiPearl completed the design of the most complex CPU ever designed in Europe, Rhea1. Featuring 80 Arm Neoverse V1 cores, with 61 billion transistors, it is currently in production at TSMC. Sipearl CPUs will equip the two first European exascale supercomputers belonging to EuroHPC JU: Rhea1 will be integrated into the JUPITER machine based in Germany and Rhea2 will be part of Alice Recoque in France.
Incubated Within The European Processor Initiative (EPI) Consortium And Seed-funded By The European Union, SiPearl Employs Almost 200 People In :
France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis)
Spain (Barcelona)
Italy (Bologna)
Following a €130 million Series A, the company has launched its Series B round.
About the role In this role,
you will work closely with our Verification Team Lead to define and drive the architecture of SiPearl’s microprocessor verification platform. You will play a key role in designing and validating our next-generation SoCs while leading a team of engineers.
What a regular day at the job might look like Define the verification platform architecture (UVM/SystemVerilog, C/C++, Python…)
Develop and maintain test environments, verification benches, and functional simulations
Plan, prioritize, and track verification activities throughout the development cycle
Lead and mentor a team of verification engineers
Collaborate with system architects, design teams, and embedded software teams.
What Would Make You Succeed In This Role Minimum 7–10 years of experience in ASIC/SoC verification, including 3–5 years as an architect or lead
Proficiency in SystemVerilog/UVM, VHDL/Verilog, C/C++, Python/TCL scripting.
Proven ex