Principal Functional Verification Engineer
Pubblicato il 21-08-2026 - Altro in Roma
The Role
As a Functional Verification Principal Engineer, you will be interfacing with architecture, de-sign, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work will involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.
Key Responsibilities
Reading and analysing the system requirements and architecture requirement documents.
Developing detailed Test and Coverage plans based on the Architecture and Micro-architec-ture.
Developing Verification Methodology, ensuring scalability and portability across environ-ments.
Developing Verification environment development and maintenance in SystemVeri-log/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regres-sions and Debug of the test failures.
Using the standard tools and flows of the verification process (Simulators, Coverage Analyz-ers, Unix, Continuous Integration, Bug Tracking, ...).
Create and execute testcases to verify the functionality, performance, and robustness in em-bedded C and SV.
Identify, isolate, and debug issues found during verification, leveraging simulation and debug-ging tools to root-cause failures and drive resolution with design and architecture teams.
Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verifi-cation activities.
Organize work and deliverables between skills, internal and external teams.
Mentoring and training the next generation of verification engineers.
Coordinating functional verification teams.
Required Skills And Experience
Master Degree in relevant field.
Min 15 years of experience in relevant field of Verification of complex SoC or IP
Experience in
SystemVerilog/UVM
SystemC/C++
Experience in