Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You write scripts because manual flows do not scale, and you speak timing signoff fluently enough to debug a failing path without waiting for translation. At Synopsys, you will work on 56G, 112G, and 224G PAM4/6 SerDes platforms that ship into real products.
Drive physical implementation of high-speed SerDes IPs and test chips from RTL to GDSII, including timing closure and physical signoff
Lead a small team of engineers through implementation flows, setting technical direction and clearing tapeout blockers
Collaborate with front-end, analog, and CAD teams to resolve analog/digital interface challenges
Automate implementation flows using Perl, Tcl,

and Python across multiple process technologies
Own chip-level integration and signoff for mixed-signal IPs before tapeout
Your implementation decisions will determine whether SerDes IPs tape out on schedule and meet power and area targets
The automation you build will reduce manual effort and improve consistency across future projects
Your technical judgment will shape how the team approaches low-power design and advanced node implementation
The SerDes platforms you help deliver will power high-speed connectivity in AI, data center, and networking products worldwide
MSEE with 10+ years or BSEE with 12+ years in digital or physical design
Experience leading physical implementation through multiple project tapeouts
Proven experience with TSMC 16nm or below, including low-power design techniques
Strong scripting skills in Perl, Tcl, or Python with CAD automation experience
Solid understanding of digital/mi

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