Physical Asic Design Implementation Engineer - Naples

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ppWe are looking for two Physical ASIC Design Implementation Engineers to strengthen our Physical Digital Implementation Group, in Naples.
One of the positions is aimed at a more senior profile, who will take on a technical lead role in larger projects.
You will work on full back-end projects, covering the complete flow from netlist-in to GDSII-out.
The role includes both top-level chip implementation and block-level designs across technology nodes.
A thorough understanding of the complete Cadence Innovus Place-and-Route flow is required.
/p h3What you will do /h3 pFor more than 25 years, imec has provided ASIC prototyping and production services to companies and universities worldwide.
Imec supports its customers in designing integrated circuits and bringing them from the initial prototype stage through to production.
Our customer base includes more than 900 universities and companies worldwide.
/p pTo further strengthen the Physical Digital Implementation Group, also known as the Back-End Group, within DSRD, we are looking for a highly motivated and experienced engineer.
/p pAs part of imec, DSRD has extensive industrial experience, strong relationships with leading semiconductor foundries, and long-standing collaborations with major EDA tool vendors and IP providers.
The unit supports customers worldwide in the design, physical implementation, prototyping, fabrication, and testing of advanced electronic products.
/p pAs a Physical ASIC Design Implementation Engineer, you will work directly with customers on future projects and contribute to the complete Cadence Innovus Place-and-Route and sign-off flow.
/p pYour responsibilities will include: /p ul liSetting up and configuring the implementation flow for the selected technology node, foundry requirements, and library set /li liSetting up and implementing low-power designs using UPF /li liPerforming floorplanning, macro placement,



and power-grid design /li liExecuting timing-driven placement and placement optimization /li liPerforming static timing analysis and design optimization for setup timing /li liImplementing Clock Tree Synthesis /li liPerforming scan-chain reordering and re-stitching /li liExecuting timing-driven routing, including signal-integrity analysis /li liPerforming in-place optimization to achieve timing closure across all required modes and corners /li liDebugging and resolving setup and hold violations /li liPerforming sign-off parasitic extraction using Quantus and generating SPEF files /li liPerforming sign-off static timing analysis using Tempus /li liPerforming sign-off power and EM/IR analysis using Voltus /li liExecuting physical verification, including DRC, ERC, LVS, and antenna checks /li liPerforming logic equivalence checking /li liSupporting final sign-off closure and tape-out /li /ul pFor hierarchical designs, you may take responsibility for design partitioning and derive timing budgets and constraints for individual sub-blocks from the top-level SDC.
You will work closely with the Physical Design Implementation Team throughout the entire chip-design cycle to drive timing, power, and physical sign-off closure for tape-out.
You will also interact directly with customers to discuss design specifications, implementation requirements, technical issues, and project status.
/p h3What we do for you /h3 pWe offer you the opportunity to join one of the world's premier research centers in nanotechnology in bNaples, Italy /b.
With your talent, passion and expertise, you'll become part of a team that makes the impossible possible.
Together, we shape the technology that will define the society of tomorrow.
/p pWe are committed to being an inclusive employer ( and proud of our open, multicultural,



and informal working environment with ample possibilities to take initiative and show responsibility.
In everything we do, your future colleagues are guided by the imec values of passion, excellence, connectedness, and integrity.
We commit to supporting and guiding you in this process, not only with words but also with tangible actions.
Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.
/p pWe are aware that your valuable contribution makes imec a top player in its field.
Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.
/p h3Who you are /h3 ul liYou hold a Master's degree in Electronics Engineering.
/li liYou have at least 8 years of experience in physical implementation, including experience with advanced technology nodes from 12 nm down to 2 nm.
/li liYou have experience with hierarchical, multi-block, and top-level chip designs.
/li liYou have strong experience with the Cadence digital implementation flow, particularly Innovus.
/li liExperience with Tempus, Quantus, and Voltus is highly desirable.
/li liYou have experience with low-power design techniques, including clock gating, multiple voltage domains, power gating, state retention, and switchable power domains.
/li liYou have strong knowledge of static timing analysis, timing closure, signal integrity, power integrity, and physical verification.
/li liYou can debug complex tool, flow, library, constraint, and design-related issues.
/li liYou have excellent communication skills and are comfortable working in an international and multicultural environment.
/li liFluency in English is required.
/li liYou enjoy interacting directly with customers and can communicate technical topics clearly and effectively.
/li libFor the senior position specifically /b: You have experience acting as Technical Lead, coordinating team members, making technical decisions, and managing implementation priorities.
/li /ul /p #J-*****-Ljbffr

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7in3pf