Principal R&D Engineer

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7jajxj

We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

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You AreYou have spent over a decade turning RTL into working silicon, and you know that the difference between a SerDes IP that meets spec and one that actually tapes out comes down to decisions made during floor planning, not during signoff.
You have taped out chips at 16nm or below. You write scripts because manual flows do not scale, and you speak timing signoff fluently enough to debug a failing path without waiting for translation. At Synopsys, you will work on 56G, 112G,



and 224G PAM4/6 SerDes platforms that ship into real products.
What You'll Be Doing
- Drive physical implementation of high-speed SerDes IPs and test chips from RTL to GDSII, including timing closure and physical signoff
- Lead a small team of engineers through implementation flows, setting technical direction and clearing tapeout blockers
- Develop timing constraints and design architectures that meet power, area, and performance targets on TSMC 16nm and below
- Collaborate with front-end, analog, and CAD teams to resolve analog/digital interface challenges
- Automate implementation flows using Perl, Tcl, and Python across multiple process technologies
- Own chip-level integration and signoff for mixed-signal IPs before tapeout

The Impact You Will Have
- Your implementation decisions will determine whether SerDes IPs tape out on schedule and meet power and area targets
- The timing constraints you create will enable succe

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7jajxj