Senior/Staff Silicon Physical Design Engineer
Pubblicato il 26-08-2026 - Axelera AI in Roma
About Us
Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.
In just four years, we have raised a total of $370 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.
We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.
Our unwavering commitment to innovation has firmly established us as a global industry pioneer.
Position Overview
As a Senior/Staff Silicon Physical Design Engineer at Axelera AI, you will play a crucial role in developing cutting-edge multi-core in-memory compute SoCs. Leveraging your expertise in ASIC Physical Design from RTL to GDS, you will be responsible for all aspects,
including synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR signoff, and formal verification. You will collaborate closely with architecture and RTL teams to ensure successful project execution.
Key Responsibilities
Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification.
Constraint generation, timing analysis and optimization.
Execute clock tree synthesis (CTS) and custom clock-building techniques.
Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.
Utilize EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
Develop automation scripts in Python, Tcl, Bash and contribute to flow development.
Debug and solve technical challenges related to physical design.
Collaborate with architecture, RTL, and verifi