Principal R&D Engineer - Enterprise SerDes Physical Implementation

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We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent over a decade turning RTL into working silicon, and you know that the difference between a SerDes IP that meets spec and one that actually tapes out comes down to decisions made during floor planning, not during signoff.

You have taped out chips at 16nm or below. You write scripts because manual flows do not scale, and you speak timing signoff fluently enough to debug a failing path without waiting for translation. At Synopsys, you will work on 56G, 112G, and 224G PAM4/6 SerDes platforms that ship into real products.

What You'll Be Doing

Drive physical implementation of high-speed SerDes IPs and test chips from RTL to GDSII, including timing closure and physical signoff

Lead a small team of engineers through implementation flows, setting technical direction and clearing tapeout blockers

Develop timing constraints and design architectures that meet power, area, and performance targets on TSMC 16nm and below

Collaborate with front-end, analog, and CAD teams to resolve analog/digital interface challenges

Automate implementation flows using Perl, Tcl, and Python across multiple process technologies

Own chip-level integration and signoff for mixed-signal IPs before tapeout The Impact You Will Have

Your implementation decisions will determine whether SerDes IPs tape out on schedule and meet power and area targets The timing constraints you create will enable successful signoff across advanced process nodes





Your leadership will accelerate the team's ability to deliver complex mixed-signal IPs without last-minute rework The automation you build will reduce manual effort and improve consistency across future projects

Your technical judgment will shape how the team approaches low-power design and advanced node implementation The SerDes platforms you help deliver will power high-speed connectivity in AI, data center, and networking products worldwide

What You'll Need

MSEE with 10+ years or BSEE with 12+ years in digital or physical design

Experience leading physical implementation through multiple project tapeouts

Deep knowledge of the full design cycle from RTL to GDSII, including chip-level integration

Proven experience with TSMC 16nm or below, including low-power design techniques

Strong scripting skills in Perl, Tcl, or Python with CAD automation experience

Solid understanding of digital/mixed-signal verification flows and SOC integration

Willingness to travel internationally as required

Who You Are

You can spot the real bottleneck in a timing report and propose a fix that does not blow up area or power

You push back on front-end teams if the RTL will create an unsolvable physical problem, and you can explain why

You make decisions without waiting for perfect information because delay costs more than a well-informed judgment call

You lead by setting clear direction and stepping in only when the team hits a blocker they cannot solve alone

You treat automation as part of the job because you have seen what happens when manual flows meet tight schedules The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/7jks2v