Lead of microelectronics design center eda support group...
Pubblicato il 28-08-2026 - Fondazione Chips-IT in Bardi
Lead of Microelectronics Design Center EDA Support Group... FONDAZIONE CHIPS-IT Pavia, Pavia Province, IT
About Fondazione Chips-IT
The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry. The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.
Missions of the Foundation
- Promote the design and development of integrated circuits
- Strengthen the system of professional training in the field of microelectronics
- Ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field
The Chips-IT Foundation is seeking a senior professional to lead and support the activities of its Microelectronics Design Center. This role is central to ensuring the efficiency, reliability, and continuous evolution of design tools, laboratory infrastructure, and the overall R&D; environment for advanced System‑on‑Chip (SoC) development.
The Lead of Microelectronics Design Center EDA Support Group will be responsible for the maintenance, optimization, and governance of Electronic Design Automation (EDA) flows, Process Design Kits (PDKs). This position serves as a technical focal point for microelectronics design infrastructure,
coordinating interactions with foundries, and EDA vendors, while enabling seamless SoC design from concept through tape‑out. The work can be carried out either in Pavia or in Bologna.
KEY RESPONSIBILITIES
- Coordinate with vendors for EDA tool procurement, licensing, and maintenance contracts.
- Maintain and optimize EDA toolchains for digital design, including simulation, synthesis, verification, and physical design.
- Manage PDK installations and updates, acting as the technical liaison with foundries for issue resolution and continuous support.
- Maintain, calibrate, and troubleshoot HW Emulators, ensuring uninterrupted research and pre-silicon verification activities.
- Enable seamless integration of PDKs into EDA workflows, supporting the full SoC design lifecycle from concept to tape‑out.
- Ensure accurate and up‑to‑date documentation of tool installations, maintenance procedures, and best practices for EDA flows and laboratory equipment.
QUALIFICATIONS
- Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field with a focus on EDA tools, PDKs, or semiconductor processes.
- Proven experience in maintaining EDA tools and managing PDKs (Cadence, Synopsys, Siemens).
- Strong understanding of semiconductor fabrication processes, including interactions with foundries.
- Familiarity with hardware description languages (Verilog, VHDL), digital and analog design workflows.
- Tape‑out experience with advanced process nodes (16nm and below).
WHAT WE OFFER
- Competitive compensation and contract type, to be negotiated based on qualifications and experience
- Possibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title.
- Lunch tickets
- Private health care coverage depending on your role and contract
- Structured growth path, with ongoing access to training and updates
- Networking opportunities with industry‑leading professionals
- International environment
- Hybrid work policy
- Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years
In conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione è compreso tra Euro 25.000,00 e 55.000,00. L'ampiezza del range è finalizzata a valutare candidature con diversi livelli di seniority; l'offerta finale sarà strettamente commisurata all'effettiva esperienza e alle competenze del candidato, e sarà integrata dai vantaggi aziendali previsti per il ruolo.
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