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Lead of Silicon Design Support Infrastructure

Pubblicato il 29-08-2026 - Altro in Bologna

The Foundation "Italian Center for the Design of Semiconductor Integrated Circuits," also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.
The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a centre of excellence in frontier research on semiconductor design, as well as a pivotal centre of the Italian semiconductor ecosystem and expertise.
Posizione
Fondazione Chips-IT is seeking a Lead of Silicon Design Support Infrastructure to establish and lead the Design, Validation and Test Infrastructure Group. This Group will enable multi-domain semiconductor demonstrator development (Digital, Analog, Power) supporting internal research teams and collaborations with university and industry partners.
The Group will have a central role in the operation of Chips-IT, providing the best possible environment for Research Groups to develop their projects.



Its capabilities should bring the Foundation to demonstration levels of TRL 5 to 7 depending on the projects, while also providing infrastructure access for academic and industrial partners within established collaboration frameworks.
The work can be carried out either in Pavia or in Bologna.
Key Responsibilities
In coordination with the Research Groups Directors, define and propose to the CEO the organisation of the Silicon Infrastructure Group and present a 3‐year budget forecast.
Together with the HR Manager, define the profiles of the personnel, engineers and technicians, to recruit (initially between 5 and 10 people).
Provide the infrastructure for: EDA Tool Management, Computing Infrastructure Optimization, Workflow Automation, Advanced Design Tools, Emulation and Pre‐Silicon Validation, Multi‐Domain Test Facility, Foundry and Fabrication Coordination.
Manage licensing and compliance, data management & security, test facility safety, technical roadmap supp

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