NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.
NXP is building new teams in Catania to create high impact microcontrollers (MCU) as part of NXP’s intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace.
This team will include all key engineering disciplines in Design, Architecture, Verification, DfT and Physical Design to produce high performance and quality products.
Your Responsibilities.
- Develop and implement efficient and comprehensive verification environments and test benches using industry-standard methodologies (e.g., UVM, SystemVerilog)

- Create detailed verification plans based on design specifications, identifying key functionalities and potential corner cases
- Develop, execute, and debug test cases to thoroughly verify the design against its specifications
- Analyze simulation results, identify discrepancies, and work closely with design engineers to resolve issues
- Develop and maintain verification collateral, including assertions, functional coverage models, and verification scripts
- Participate in verification reviews, contributing to the improvement of verification methodologies and processes
- Collaborate with design, architecture, and software teams throughout the product development lifecycle

Your Profile.
- Master’s degree in electronic engineering, Computer Engineering, or a related field
- Proven experience (typically 5+ years) in digital IC design verification
- Capability to execute the assigned tasks with minimum support
- Strong

Senior Principal Digital Verification Engineer

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