Digital Design Engineer
Pubblicato il 30-08-2026 - Elettrotecnica in Italia
NXP's Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP's advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.
NXP is building new teams in Catania to create high impact micro-controllers (MCU) as part of NXP's intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class ICs at a world class pace. This team will include all key engineering disciplines in Analog and Digital Design, Architecture definition, Verification, DfT and Physical Design to produce high performance and quality products.
Your Responsibilities Develop digital sub-circuits related to complex System-on-Chip (SOC) based on pre-defined specification, RTL coding (Verilog/SystemVerilog), synthesis,
static timing analysis (STA), formal verification, and power analysis competences.
Contribute to design for testability (DFT) implementation and verification, debugging skills.
Collaborate closely with analog, mixed-signal, and software teams to define interfaces, optimize system performance and ensure seamless integration.
Follow design methodologies shared among the team to guarantee time schedule and satisfy quality targets criteria.
Perform comprehensive design verification using simulation tools, formal verification techniques, and hardware emulation.
Participate in post-silicon validation and debug activities, identifying and resolving issues to ensure product quality.
Generate detailed design documentation, including specifications, test plans, and design reviews.
Stay abreast of industry trends, emerging technologies, and best practices in digital IC design methodology shared in the team.
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