Principal HS Digital Design Engineer

30 ago - Pavia
ams OSRAM

Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC productsLead RTL development and integrationDrive design reviews and quality standardsSupport verification and implementation teamsMSc or PhD in Electrical Engineering10+ years digital IC design experienceHigh-speed digital IC design experience for communication or mixed-signal SoC products is required; knowledge of high-speed interfaces such as UCIe, PCIe or similar protocols is an advantageInterface protocols and clock-domain crossingSynthesis and timing analysisAdvanced CMOS node experience, including FinFET and/or FD-SOI, is requiredJob descriptionTechnical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC productsDefine digital subsystem architecturesLead RTL development and integrationDrive design reviews and quality standardsSupport verification and implementation teamsMentor design engineersProfile descriptionMSc or PhD in Electrical Engineering10+ years digital IC design experienceRTL design (Verilog/SystemVerilog)High-speed digital IC design experience for communication or mixed-signal SoC products is required; knowledge of high-speed interfaces such as UCIe, PCIe or similar protocols is an advantageInterface protocols and clock-domain crossingSynthesis and timing analysisAdvanced CMOS node experience, including FinFET and/or FD-SOI, is requiredWe offerams OSRAM is an Equal Employment Opportunity Employer. Diversity, equity and inclusion is strongly established in our corporate culture and we firmly believe it makes us more successful as a company. All qualified applications will receive consideration for employment regardless of ethnic, national or social origin, gender, gender identity, sexual orientation, color, religion, age, physical and mental abilities.Stefanie (email hidden)ind out more about us at:
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