FPGA Architect – High-Speed Networking

30 ago - Pistoia
Luxoft

We're hiring: Principal FPGA Engineer – Communications Test & Measurement
Location: Turin, Italy, or remote within Italy (depending on the selected candidate's location)
We are looking for an experienced Principal FPGA Engineer to join an international team developing next-generation communications test, monitoring and assurance solutions for the telecommunications, cloud, aerospace, defence, railway and industrial sectors.
This is an opportunity to take ownership of the complete FPGA architecture of cutting-edge products and to work on high-performance, multi-gigabit designs in a highly innovative environment.
Your responsibilities
✔ Define and drive end-to-end FPGA architecture.
✔ Lead architecture decisions, IP selection, floor-planning strategies and timing closure activities.
✔ Act as the main technical reference point for FPGA design and debugging activities.
✔ Mentor engineers and support system integration and board bring-up activities.
✔ Collaborate closely with global engineering teams.
Required qualifications and experience




✔ Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field.
✔ Excellent experience in FPGA design and architecture .
✔ Extensive hands-on experience with Verilog, SystemVerilog and/or VHDL .
✔ Strong expertise in m ulti-Gbps SerDes, transceivers, PLLs and high-speed Ethernet technologies.
✔ Experience with optical interfaces and modules (SFP, QSFP).
✔ Knowledge of networking protocols, including VLAN, MPLS, VPLS, VoIP and IPTV.
✔ Solid experience with AMD/Xilinx or Altera FPGA platforms.
✔ Experience with formal verification methodologies and UVM.
✔ Experience with Git and collaborative development environments.
Nice to have
➕ Publications or patents related to FPGA design, DSP or high-speed digital systems.
➕ Experience with PCIe, DSP systems and high-speed digital board design.
➕ Familiarity with Siemens Questa, Aldec Riviera or similar tools.
➕ Experience using AI-based tools to support FPGA d

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