Vacature: DESIGNER
Pubblicato il 01-09-2026 - SIAE MICROELETTRONICA in Italia
Join SIAE MICROELETTRONICA and be part of an innovative and transformative journey at the heart of global telecommunications As a global leader in advanced wireless and optical networking solutions, we drive connectivity for millions across the globe, from urban centers to remote locations. Our systems power networks keep more than a billion people connected worldwide, whether they're chatting with smartphones, connecting businesses or supporting critical infrastructure. We are in a dynamic transformation phase, fueled by National and European investments in 5G, 6G, AI and O-RAN. Our R&D; powerhouse, representing half of the company, is pioneering future connectivity technologies that will redefine digital infrastructure. Joining us means you'll work with top‐tier professionals, engage in groundbreaking projects, and experience unparalleled growth opportunities.
You will have the unique opportunity to contribute to several projects that will shape the future of telecommunications, with mentorship and coaching from industry leaders. At SIAE MICROELETTRONICA,
we embrace a collaborative culture that encourages personal growth and celebrates innovation. Whether we're optimizing microelectronics for high‐density integrations, creating new optical transmission solutions or building energy‐efficient systems, our commitment to excellence is unwavering.
If you are driven by purpose, excited about innovation, and passionate about building a connected future, we'd love to have you join us About the Role As an FPGA Designer, you will join the R&D; Digital Design team and contribute to the development of FPGA/ASIC‐based processing modules for broadband telecom systems — including packet processing, synchronization, and timing architectures.
You will transform system‐level requirements into efficient, high‐performance logic implementations, working closely with system engineering, hardware, and embedded firmware teams. This role offers hands‐on involvement across the full FPGA deve