03 set - Italia
Altro
Experteer Italy is seeking a Mixed Signal Verification engineer in Catania to verify analog/mixed-signal IPs and build SV Real Number and Verilog-AMS models for analog blocks. You will collaborate with designers and systems engineers to validate architecture, test modes, and DFT strategies with focus on robust verification.
The role requires a strong background in analog and mixed-signal fundamentals, proficiency in Verilog/SystemVerilog/Verilog-AMS/Verilog-A, and 2+ years of related experience,
J-18808-Ljbffr
05 set - Siena
Festival del Calcio Italiano
05 set - Torino
Sit
05 set - Torino
Quest Global
05 set - Ostiglia
Adecco