Analog Mixed-Signal Verification Engineer
Pubblicato il 05-09-2026 - Inventvm Semiconductor in Milano
INVENTVM is actively looking for a talented AMS Verification Engineer to join the design team.
Massimizzi le sue possibilità di successo assicurandosi che il suo CV e le sue competenze corrispondano ai requisiti di questa posizione.
In this role, you will be responsible for verifying mixed-signal and analog/mixed-signal (AMS) integrated circuits by developing robust verification environments, creating testbenches, and ensuring first-pass silicon success. You will work closely with analog and digital designers throughout the product development cycle.
Key Responsibilities
- Develop and execute verification plans for analog and mixed-signal IPs and SoCs
- Create, maintain, and enhance AMS verification environments using industry-standard methodologies
- Develop behavioral models of analog blocks using Verilog-A, Verilog-AMS, SystemVerilog RNM, or equivalent modeling languages
- Design testbenches, stimuli, checkers, assertions, and coverage metrics to validate mixed-signal functionality
- Perform functional, corner, Monte Carlo, and regression simulations
- Collaborate with analog and digital design teams to identify, debug, and resolve functional issues
- Support integration and verification of analog IPs within larger digital or mixed-signal SoCs
- Analyze simulation results and communicate findings through clear technical reports
- Contribute to verification methodology improvements, automation, and scripting
- Support silicon bring-up and correlation between simulation and laboratory measurements when required
Required Qualifications
- Master's degree in Electrical Engineering, Electronics Engineering, or a related field
- Solid understanding of analog and mixed-signal circuit fundamentals, including:
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Operational amplifiers
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Comparators
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ADCs and DACs
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PLLs (preferred)
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Voltage regulators and references
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Switched-capacitor circuits
- Experience with AMS simulation and verification tools (e.G., Cadence Virtuoso, Spectre, Xcelium)
- Knowledge of Verilog-AMS, Verilog-A, SystemVerilog, or Real Number Modeling (RNM)
- Familiarity with scripting languages such as Python, Tcl, Perl, or Shell
- Strong debugging and problem-solving skills
- Good communication skills and ability to work effectively in cross-functional teams
Fluent in English
Desirable Qualifications
Experience with UVM-based verification environments.
- Knowledge of digital verification methodologies.
- Familiarity with mixed-signal modeling techniques and abstraction levels.
- Experience with low-power verification concepts.
- Understanding of CMOS device operation and semiconductor fundamentals. xykwogc
All INVENTVM positions offer a stake in the company equity that also entitles to receive dividends, competitive benefits, sustainable work logistics aimed at balancing personal life and project deadlines.