Lead Of Microelectronics Design Center Eda Support Group
Pubblicato il 03-09-2026 - Fondazione Chips-IT in Bardi
ph3About Fondazione Chips-IT /h3 pThe Foundation "Italian Center for the Design of Semiconductor Integrated Circuits," also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.
The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.
/p ul liPromote the design and development of integrated circuits /li liStrengthen the system of professional training in the field of microelectronics /li liEnsure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field /li /ul h3Position /h3 pThe Chips-IT Foundation is seeking a senior professional to lead and support the activities of its Microelectronics Design Center.
This role is central to ensuring the efficiency, reliability, and continuous evolution of design tools, laboratory infrastructure, and the overall RD environment for advanced System-on-Chip (SoC) development.
The Lead of Microelectronics Design Center EDA Support Group will be responsible for the maintenance, optimization, and governance of Electronic Design Automation (EDA) flows and Process Design Kits (PDKs).
This position serves as a technical focal point for microelectronics design infrastructure, coordinating interactions with foundries and EDA vendors, while enabling seamless SoC design from concept through tape?out.
The work can be carried out either in Pavia or in Bologna.
/p h3Key Responsibilities /h3 ul liCoordinate with vendors for EDA tool procurement, licensing, and maintenance contracts /li liMaintain and optimize EDA toolchains for digital design, including simulation, synthesis, verification, and physical design /li liManage PDK installations and updates,
acting as the technical liaison with foundries for issue resolution and continuous support /li liMaintain, calibrate, and troubleshoot hardware emulators, ensuring uninterrupted research and pre?silicon verification activities /li liEnable seamless integration of PDKs into EDA workflows, supporting the full SoC design lifecycle from concept to tape?out /li liEnsure accurate and up?to?date documentation of tool installations, maintenance procedures, and best practices for EDA flows and laboratory equipment /li /ul h3Requirements /h3 ul liMaster's degree in Electrical Engineering, Computer Engineering, or a closely related field with a focus on EDA tools, PDKs, or semiconductor processes /li liProven experience in maintaining EDA tools and managing PDKs (Cadence, Synopsys, Siemens) /li liStrong understanding of semiconductor fabrication processes, including interactions with foundries /li liFamiliarity with hardware description languages (Verilog, VHDL) and digital and analog design workflows /li liTape?out experience with advanced process nodes (16nm and below) /li /ul h3Benefits /h3 ul liCompetitive compensation based on qualifications and experience /li liOpportunity to enter a PhD program while working /li liLunch tickets /li liPrivate health care coverage dependent on role and contract /li liStructured growth path with ongoing training and updates /li liNetworking opportunities with industry?leading professionals /li liInternational environment /li liHybrid work policy /li liTax deductions for eligible candidates (up to 90% for 6 to 13 years) /li liIn conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione è compreso tra Euro ******,00 e ******,00.
L'ampiezza del range è finalizzata a valutare candidature con diversi livelli di seniority; l'offerta finale sarà strettamente commisurata all'effettiva esperienza e alle competenze del candidato, e sarà integrata dai vantaggi aziendali previsti per il ruolo.
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