You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow, doing implementation to achieve best in class ASICs, which are optimized for power, performance and area metrics.NION2026 Some of our benefits: Flexible and hybrid working schemesA minimum of 90 days of Maternity and Paternity Leave, with the option to return to work within a year following the birth or adoption of a child (based on eligibility)Life insurance to all employees to provide peace of mind and financial securityWell-being programs to support your mental and physical healthOpportunities to join and receive support from Nokia Employee Resource Groups (NERGs)Employee Growth Solutions to support your personalized career & skills developmentDiverse pool of Coaches & Mentors to whom you have easy accessA learning environment which promotes personal growth and professional development - for your role and beyondLearn about additional benefits in specific countries. 3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodesHas solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design,

implementation flows and methodologies for deep submicron designExperience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar, PV tools like Calibre and IR tools like RedhawkScripting experience in TCL, python or PerlCandidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academicsPerform physical implementation steps including floor planning, place and route, power/clock distribution,

physical verification and timing closure at block level as well as full chipWork with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closurePerform technical evaluations of IP vendors, process nodes

and provide recommendationsDevelop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSIIPerform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-offPerform Physical verification and IR/EM analysis on blocks as well as top

Full timePosting Date: 2026-09-03

SoC Physical Design Engineer

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